一种利用钨作一级互连的亚微米三电平金属栅阵列工艺

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI:10.1109/VMIC.1989.78074

P. Manos, F. Pintchovski, J. Klein, E. Travis, B. Boeck, M. Woo, C. Chen, S. Koenigseder, R. Dillard

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引用次数: 3

摘要

一种新的三级金属工艺，利用钨进行一级金属化，已开发用于亚微米阵列。接触屏障是溅射TiN和CVD TiN的复合层，提供了良好的涂层钨层的附着力。其他工艺模块包括锥形接触和通过蚀刻，用于细线图案的染色抗蚀剂，用于第一次ILD和via-1的回流BPSG，以及低应力氮化钝化，为所有三层提供无空洞的金属化。利用该技术已制造出1.0 μ m栅极阵列的原型。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A submicron triple-level-metal gate array process utilizing tungsten for 1st level interconnect

A novel triple-level-metal process, utilizing tungsten for first-level metallization, has been developed for use in submicron arrays. The contact barrier is a composite layer of sputtered and CVD TiN, providing for good adhesion of the blanket tungsten layer. Other process modules include tapered contact and via etches, dyed resist for fine-line patterning, reflowed BPSG for first ILD and via-1, and low-stress nitride passivation, providing for void-free metallization for all three layers. Prototype 1.0- mu m gate arrays have been fabricated using this technology.<>

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Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference

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