{"title":"超导数字电子器件中支持vlsi的EDA工具的进展","authors":"S. Whiteley, J. Kawa","doi":"10.1109/ISEC46533.2019.8990931","DOIUrl":null,"url":null,"abstract":"Synopsys is developing a complete design flow tool set for use with superconductive digital logic, initially focusing on ERSFQ and AQFP technologies. This flow begins with design synthesis of a high level logic description, automating cell placement, routing, and design validation. Circuit simulation and statistical analysis tools utilizing advanced TCAD techniques are also under development. The flow will provide a tool set to address all requirements culminating with a tape-out. The proposed flow will parallel the functionality used routinely in the semiconductor industry, but is still at a very early stage of development for superconductors.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Progress Toward VLSI-Capable EDA Tools for Superconductive Digital Electronics\",\"authors\":\"S. Whiteley, J. Kawa\",\"doi\":\"10.1109/ISEC46533.2019.8990931\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Synopsys is developing a complete design flow tool set for use with superconductive digital logic, initially focusing on ERSFQ and AQFP technologies. This flow begins with design synthesis of a high level logic description, automating cell placement, routing, and design validation. Circuit simulation and statistical analysis tools utilizing advanced TCAD techniques are also under development. The flow will provide a tool set to address all requirements culminating with a tape-out. The proposed flow will parallel the functionality used routinely in the semiconductor industry, but is still at a very early stage of development for superconductors.\",\"PeriodicalId\":250606,\"journal\":{\"name\":\"2019 IEEE International Superconductive Electronics Conference (ISEC)\",\"volume\":\"88 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE International Superconductive Electronics Conference (ISEC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISEC46533.2019.8990931\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Superconductive Electronics Conference (ISEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISEC46533.2019.8990931","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Progress Toward VLSI-Capable EDA Tools for Superconductive Digital Electronics
Synopsys is developing a complete design flow tool set for use with superconductive digital logic, initially focusing on ERSFQ and AQFP technologies. This flow begins with design synthesis of a high level logic description, automating cell placement, routing, and design validation. Circuit simulation and statistical analysis tools utilizing advanced TCAD techniques are also under development. The flow will provide a tool set to address all requirements culminating with a tape-out. The proposed flow will parallel the functionality used routinely in the semiconductor industry, but is still at a very early stage of development for superconductors.