SLCFET Technology: Current Progress and Future Directions for Monolithically Integrated Low Loss Switches with High Performance Amplifiers

Next generation RF systems require RF components capable of maintaining their performance across increasingly wide, multiple octave frequency bandwidths, supporting the operational flexibility and adaptability that is a primary feature of the direct signal conversion based digital back-ends of these architectures. The Superlattice Castellated Feld Effect Transistor (SLCFET) uses stacked AlGaN/GaN heterojunctions that have been etched into parallel nanoribbons between source and drain, in combination with a three dimensional gate structure providing control of the resulting transistor by simultaneously addressing the charge in each individual 2DEG layer of the stacked heterostructures through the sidewalls of the nanoribbons. The device structure of the SLCFET was specifically engineered as a solution to the limits of RF switch performance in FETs that inhibits wideband RF switch based circuit performance, due to the SLCFET topology’s inherent capability of decoupling the transistor’s ON resistance from its OFF capacitance [1] . Since this technology’s first appearance in publication [2] , the process has matured and been extended, with both 6-channel and 10 channel heterostructure based transistors and RF switch MMICs demonstrated [3] , and the 6-channel RF switch process having been qualified and productized, Fig. 1 [4] . The flexibility and broad capabilities of the SLCFET technology as both a high power switch and a low loss, high linearity, fast switching technology have subsequently been demonstrated using this production RF switch process. The high power handling and switching capability of the SLCFET was demonstrated, with a low loss and high isolation 0.1–4 GHz 100W SPDT switch [5] , while the fast switching, high linearity capabilities of the SLCFET were highlighted by the demonstration of a 0.4–2 GHz reconfigurable bandpass filter [6] . The 100W SPDT design demonstrated 10x greater isolation along with ~10% improvement in loss while requiring a ~37% smaller MMIC size than a GaN SPDT designed for the same frequency and power level built using a commercial conventional device process, Fig. 2 . The reconfigurable filter provides over 500 different filter channels, with variable bandwidth and center frequencies, Fig. 3 , all integrated into a single integrated circuit, providing an average of 2 dB improvement for each filter channel in NF and insertion loss, along with ~40x more power handling and ~20x greater linearity than an identical filter built using a state-of-the-art GaAs pHEMT process.