通过选择性外延生长实现半介电器件隔离的双极结构

K. O, H. Lee, R. Reif, W. Frank, W. Metz, T. Gillis
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引用次数: 6

摘要

在选择性外延层上制备了估计f/sub /为5 GHz的双极结构。从注入砷的多晶硅层中扩散砷原子形成浅埋层(0.25 μ m,约0.50 μ m)。多晶硅层通过将其转化为氧化物并蚀刻氧化物来去除。通过等离子体蚀刻步骤去除选择性外延层边缘的缺陷区域,形成无缺陷的基底-集电极结;结可以放置在距离边缘小于2 μ m的地方,而不会降低器件的特性。利用选择性外延生长、LOCOS隔离和浅埋层,实现了半介电晶体管隔离。
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A bipolar structure with semi-dielectric device isolation by selective epitaxial growth
A bipolar structure with an estimated f/sub T/ of 5 GHz was fabricated on a selective epitaxial layer. A shallow buried layer (0.25 mu m approximately 0.50 mu m) was formed by diffusing arsenic atoms from an arsenic-implanted polysilicon layer. The polysilicon layer was removed by converting it to oxide and etching the oxide. The defective regions at the edges of the selective epitaxial layer were removed by a plasma etch step to form defect-free base-collector junctions; the junctions can be placed less than 2 mu m from the edges without degrading the device characteristics. Using the selective epitaxial growth, LOCOS isolation and the shallow buried layer, semi-dielectric transistor isolation was achieved.<>
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The best-case power-delay products for polysilicon-contacted bipolar-transistor gates. A theoretical study The effect of emitter sidewall isolation on the emitter junction in a double layer polysilicon bipolar process Delay analysis for BiCMOS drivers Comparing techniques for fabrication polysilicon contacted emitter bipolar transistors Thin base formation by double diffused polysilicon technology
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