{"title":"用于嵌入在2亿设备双CPU SoC上的加密应用的双真随机数生成器","authors":"V. V. Kaenel, T. Takayanagi","doi":"10.1109/CICC.2007.4405730","DOIUrl":null,"url":null,"abstract":"Implementations of a thermal noise and a chaotic True Random Number Generator (TRNG) are presented. They are embedded in a large commercial SoC and used for cryptographic applications (SSL and key generation). Their outputs are combined to improve the randomness of the bit stream. The design goal was to minimize the effect of data dependent noise injected by the supplies and substrate. The random bit rate is 2Mbit/s and passes the DIEHARD test suite. The area of the TRNG is 0.21mm2 in a 65nm CMOS process.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"24","resultStr":"{\"title\":\"Dual True Random Number Generators for Cryptographic Applications Embedded on a 200 Million Device Dual CPU SoC\",\"authors\":\"V. V. Kaenel, T. Takayanagi\",\"doi\":\"10.1109/CICC.2007.4405730\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Implementations of a thermal noise and a chaotic True Random Number Generator (TRNG) are presented. They are embedded in a large commercial SoC and used for cryptographic applications (SSL and key generation). Their outputs are combined to improve the randomness of the bit stream. The design goal was to minimize the effect of data dependent noise injected by the supplies and substrate. The random bit rate is 2Mbit/s and passes the DIEHARD test suite. The area of the TRNG is 0.21mm2 in a 65nm CMOS process.\",\"PeriodicalId\":130106,\"journal\":{\"name\":\"2007 IEEE Custom Integrated Circuits Conference\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"24\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2007.4405730\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2007.4405730","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Dual True Random Number Generators for Cryptographic Applications Embedded on a 200 Million Device Dual CPU SoC
Implementations of a thermal noise and a chaotic True Random Number Generator (TRNG) are presented. They are embedded in a large commercial SoC and used for cryptographic applications (SSL and key generation). Their outputs are combined to improve the randomness of the bit stream. The design goal was to minimize the effect of data dependent noise injected by the supplies and substrate. The random bit rate is 2Mbit/s and passes the DIEHARD test suite. The area of the TRNG is 0.21mm2 in a 65nm CMOS process.