An AI approach to timing analysis and optimization for standard cell based ASICs

An artificial-intelligence (AI)-based timing analysis and standard cell optimization CAD tool, TASCO, for standard cell-based circuits is described. TASCO executes a circuit timing analysis, finds the critical paths, the critical gates responsible, and optimizes the critical gates. It has done this in less than 60 minutes for most circuits, depending on the complexity of the circuit and how far the original circuit was from meeting the timing requirement. The only limitation encountered with the tool is a circuit complexity constraint in C-Prolog. Regardless, TASCO should prove to be a significant boost toward the goal of automating the timing verification phase of a standard cell-based design. This approach shortens the design interval and relieves the designer from a tedious and repetitive analysis.<>