{"title":"4H-SiC MOS电容器中电荷保持时间与界面缺陷和外加栅极电压的关系","authors":"K. Cheong, S. Dimitrijev, J. Han, H. B. Harrison","doi":"10.1109/COMMAD.2002.1237304","DOIUrl":null,"url":null,"abstract":"In this paper, we have investigated factors that affect the charge-retention time in 4H-SiC MOS capacitors, used as nonvolatile random-access memory elements. The charge-retention time is extracted from high temperature capacitance-transient (C-t) measurements. The SiC-SiO/sub 2/ interface traps, that relate to gate oxide processing conditions and the applied gate voltage (V/sub G/) as the main operation-related parameter are investigated. It is found that (1) the charge-retention time depends strongly on the interface-trap density and (2) the time is shortened when the applied gate voltage is reduced.","PeriodicalId":129668,"journal":{"name":"2002 Conference on Optoelectronic and Microelectronic Materials and Devices. COMMAD 2002. Proceedings (Cat. No.02EX601)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Dependence of charge-retention time in 4H-SiC MOS capacitors on interface defects and applied gate voltage\",\"authors\":\"K. Cheong, S. Dimitrijev, J. Han, H. B. Harrison\",\"doi\":\"10.1109/COMMAD.2002.1237304\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we have investigated factors that affect the charge-retention time in 4H-SiC MOS capacitors, used as nonvolatile random-access memory elements. The charge-retention time is extracted from high temperature capacitance-transient (C-t) measurements. The SiC-SiO/sub 2/ interface traps, that relate to gate oxide processing conditions and the applied gate voltage (V/sub G/) as the main operation-related parameter are investigated. It is found that (1) the charge-retention time depends strongly on the interface-trap density and (2) the time is shortened when the applied gate voltage is reduced.\",\"PeriodicalId\":129668,\"journal\":{\"name\":\"2002 Conference on Optoelectronic and Microelectronic Materials and Devices. COMMAD 2002. Proceedings (Cat. No.02EX601)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Conference on Optoelectronic and Microelectronic Materials and Devices. COMMAD 2002. Proceedings (Cat. No.02EX601)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/COMMAD.2002.1237304\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Conference on Optoelectronic and Microelectronic Materials and Devices. COMMAD 2002. Proceedings (Cat. No.02EX601)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/COMMAD.2002.1237304","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Dependence of charge-retention time in 4H-SiC MOS capacitors on interface defects and applied gate voltage
In this paper, we have investigated factors that affect the charge-retention time in 4H-SiC MOS capacitors, used as nonvolatile random-access memory elements. The charge-retention time is extracted from high temperature capacitance-transient (C-t) measurements. The SiC-SiO/sub 2/ interface traps, that relate to gate oxide processing conditions and the applied gate voltage (V/sub G/) as the main operation-related parameter are investigated. It is found that (1) the charge-retention time depends strongly on the interface-trap density and (2) the time is shortened when the applied gate voltage is reduced.