具有像素率时钟的8*8离散余弦变换芯片

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186139

L. D'Luna, W.A. Cook, R. Guidash, G.W. Brown, T. Tredwell, J. Fischer, T. Tarn

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引用次数: 3

摘要

图像压缩是满足图像数据存储和传输要求的常用手段。一种方法是在8*8图像块上使用二维离散余弦变换(DCT)进行变换域压缩。描述了一种2 μ m CMOS芯片，该芯片使用不超过像素率的时钟实时计算这种转换。该体系结构使用分布式算法处理方案来计算两个一维变换，并插入一个非常规矩阵转置RAM。描述了设计方法，包括布局，仿真，验证和测试，使用硅编译器工具集。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An 8*8 discrete cosine transform chip with pixel rate clocks

Image compression is an established means of meeting storage and transmission requirements for image data. One method is transform domain compression using the two-dimensional discrete cosine transform (DCT) on 8*8 image blocks. A 2- mu m CMOS chip that computes this transform in real-time using clocks that are no faster than the pixel rate is described. The architecture uses a distributed arithmetic processing scheme to compute two one-dimensional transforms interposed with an unconventional matrix transpose RAM. The design methodology that includes layout, simulation, verification and test, using a silicon compiler tool-set, is described.<>

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

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