{"title":"基于知识的STAP算法的新型信号处理架构[雷达SIGPRO]","authors":"M. French, Jinwoo Suh, J. Damoulakis, S. Crago","doi":"10.1109/NRC.2004.1316454","DOIUrl":null,"url":null,"abstract":"New algorithms are being developed in the radar community that blend a priori knowledge source processing with traditional digital signal processing concepts. This operational blend necessitates a system-level architecture capable of delivering both high processing throughput and memory bandwidth. This paper derives these system parameters from the knowledge aided pre-whitening algorithm and evaluates the performance of two high performance embedded computing architectures, the Imagine and Raw processors, on these kernels. The implementation results are compared with the measured performance of a conventional system based on the PowerPC with Altivec. The results show these processors exhibit significant improvements over conventional systems and that each architecture has its own strengths and weaknesses.","PeriodicalId":268965,"journal":{"name":"Proceedings of the 2004 IEEE Radar Conference (IEEE Cat. No.04CH37509)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Novel signal processing architectures for knowledge-based STAP algorithms [radar SIGPRO]\",\"authors\":\"M. French, Jinwoo Suh, J. Damoulakis, S. Crago\",\"doi\":\"10.1109/NRC.2004.1316454\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"New algorithms are being developed in the radar community that blend a priori knowledge source processing with traditional digital signal processing concepts. This operational blend necessitates a system-level architecture capable of delivering both high processing throughput and memory bandwidth. This paper derives these system parameters from the knowledge aided pre-whitening algorithm and evaluates the performance of two high performance embedded computing architectures, the Imagine and Raw processors, on these kernels. The implementation results are compared with the measured performance of a conventional system based on the PowerPC with Altivec. The results show these processors exhibit significant improvements over conventional systems and that each architecture has its own strengths and weaknesses.\",\"PeriodicalId\":268965,\"journal\":{\"name\":\"Proceedings of the 2004 IEEE Radar Conference (IEEE Cat. No.04CH37509)\",\"volume\":\"67 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-04-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2004 IEEE Radar Conference (IEEE Cat. No.04CH37509)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NRC.2004.1316454\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2004 IEEE Radar Conference (IEEE Cat. No.04CH37509)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NRC.2004.1316454","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Novel signal processing architectures for knowledge-based STAP algorithms [radar SIGPRO]
New algorithms are being developed in the radar community that blend a priori knowledge source processing with traditional digital signal processing concepts. This operational blend necessitates a system-level architecture capable of delivering both high processing throughput and memory bandwidth. This paper derives these system parameters from the knowledge aided pre-whitening algorithm and evaluates the performance of two high performance embedded computing architectures, the Imagine and Raw processors, on these kernels. The implementation results are compared with the measured performance of a conventional system based on the PowerPC with Altivec. The results show these processors exhibit significant improvements over conventional systems and that each architecture has its own strengths and weaknesses.