{"title":"CML III双极标准细胞库","authors":"B. Tufte","doi":"10.1109/BIPOL.1988.51073","DOIUrl":null,"url":null,"abstract":"A 1.25 mu m current mode logic (CML) bipolar standard cell library with subnanosecond loaded gate delays is discussed. Unique computer-aided design CAD tools that produce accurate models of the library cells and optimize designs for area, speed, and power are also discussed. The interplay between the library and the tools can produce higher speed, lower power chips, at less cost.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"CML III bipolar standard cell library\",\"authors\":\"B. Tufte\",\"doi\":\"10.1109/BIPOL.1988.51073\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1.25 mu m current mode logic (CML) bipolar standard cell library with subnanosecond loaded gate delays is discussed. Unique computer-aided design CAD tools that produce accurate models of the library cells and optimize designs for area, speed, and power are also discussed. The interplay between the library and the tools can produce higher speed, lower power chips, at less cost.<<ETX>>\",\"PeriodicalId\":302949,\"journal\":{\"name\":\"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-09-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.1988.51073\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1988.51073","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.25 mu m current mode logic (CML) bipolar standard cell library with subnanosecond loaded gate delays is discussed. Unique computer-aided design CAD tools that produce accurate models of the library cells and optimize designs for area, speed, and power are also discussed. The interplay between the library and the tools can produce higher speed, lower power chips, at less cost.<>