CML III双极标准细胞库

B. Tufte
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引用次数: 2

摘要

讨论了一个具有亚纳秒负载门延迟的1.25 μ m电流模式逻辑(CML)双极标准单元库。独特的计算机辅助设计CAD工具,产生准确的模型库细胞和优化设计的面积,速度和功率也进行了讨论。库和工具之间的相互作用可以产生更高的速度,更低的功耗芯片,以更低的成本
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CML III bipolar standard cell library
A 1.25 mu m current mode logic (CML) bipolar standard cell library with subnanosecond loaded gate delays is discussed. Unique computer-aided design CAD tools that produce accurate models of the library cells and optimize designs for area, speed, and power are also discussed. The interplay between the library and the tools can produce higher speed, lower power chips, at less cost.<>
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The best-case power-delay products for polysilicon-contacted bipolar-transistor gates. A theoretical study The effect of emitter sidewall isolation on the emitter junction in a double layer polysilicon bipolar process Delay analysis for BiCMOS drivers Comparing techniques for fabrication polysilicon contacted emitter bipolar transistors Thin base formation by double diffused polysilicon technology
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