{"title":"板级BIST的HDL方法","authors":"G. Alves, M. Gericota, J. L. Ramalho, J. Ferreira","doi":"10.1109/EURDAC.1993.410669","DOIUrl":null,"url":null,"abstract":"Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is, however, still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analyzed, and a corresponding set of testability blocks is proposed. A high flexibility and reduced cost solution is described, which implements these blocks on medium-complexity PLDs (programmable logic devices), using a simple and powerful HDL (hardware design language).<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An HDL approach to board-level BIST\",\"authors\":\"G. Alves, M. Gericota, J. L. Ramalho, J. Ferreira\",\"doi\":\"10.1109/EURDAC.1993.410669\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is, however, still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analyzed, and a corresponding set of testability blocks is proposed. A high flexibility and reduced cost solution is described, which implements these blocks on medium-complexity PLDs (programmable logic devices), using a simple and powerful HDL (hardware design language).<<ETX>>\",\"PeriodicalId\":339176,\"journal\":{\"name\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-09-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EURDAC.1993.410669\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1993.410669","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is, however, still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analyzed, and a corresponding set of testability blocks is proposed. A high flexibility and reduced cost solution is described, which implements these blocks on medium-complexity PLDs (programmable logic devices), using a simple and powerful HDL (hardware design language).<>
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