QRS/BIST:可靠的心率监测专用集成电路

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186186

S. Roy, H. Nagle, M.G. McNamer, W. Krakow

{"title":"QRS/BIST:可靠的心率监测专用集成电路","authors":"S. Roy, H. Nagle, M.G. McNamer, W. Krakow","doi":"10.1109/ASIC.1990.186186","DOIUrl":null,"url":null,"abstract":"The design of a real-time heart rate monitor implemented as a single application-specific integrated circuit (ASIC) is presented. The goal of the project was to implement a QRS detection algorithm into a single-chip environment. The testability strategies used to increase device reliability, including the implementation of built-in-self test (BIST) features, are described.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"QRS/BIST: a reliable heart rate monitor ASIC\",\"authors\":\"S. Roy, H. Nagle, M.G. McNamer, W. Krakow\",\"doi\":\"10.1109/ASIC.1990.186186\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design of a real-time heart rate monitor implemented as a single application-specific integrated circuit (ASIC) is presented. The goal of the project was to implement a QRS detection algorithm into a single-chip environment. The testability strategies used to increase device reliability, including the implementation of built-in-self test (BIST) features, are described.<<ETX>>\",\"PeriodicalId\":126693,\"journal\":{\"name\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1990.186186\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186186","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

介绍了一种用专用集成电路(ASIC)实现的实时心率监测仪的设计。该项目的目标是在单芯片环境中实现QRS检测算法。描述了用于提高设备可靠性的可测试性策略，包括实现内置自检(BIST)功能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

QRS/BIST: a reliable heart rate monitor ASIC

The design of a real-time heart rate monitor implemented as a single application-specific integrated circuit (ASIC) is presented. The goal of the project was to implement a QRS detection algorithm into a single-chip environment. The testability strategies used to increase device reliability, including the implementation of built-in-self test (BIST) features, are described.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

自引率

0.00%

发文量

期刊最新文献

A development system for an SRAM-based user-reprogrammable gate array Automated CAE tools for full custom design of bipolar analog ASICs A 200 MHz 100 K ECL output buffer for CMOS ASICs Multi circular buffer controller chip for advanced ESM system Rapid prototyping, is there an educational dilemma? (ASIC design)