An on-chip binning sensor for low-cost and accurate speed binning

Due to process variations at the very low technology nodes, the manufactured chips are grouped into different speed bins. Currently, various types of maximum operation frequency (Fmax) tests are performed for efficient speed binning by applying complex functional or structural test patterns, which incurs high test cost. In this paper, a novel on-chip Binning Sensor is proposed which can monitor the worst-case timing slack in the DUT. Then the chip can be binned to the corresponding speed bin according to the test frequency and slack information. The proposed sensor has been implemented on various ITC benchmarks and the FGU of OpenSPARCT2 core on 28nm technology node. Experiment result shows that the proposed sensor can accurately monitor the slack of the DUT with low test time. At the same time, the proposed sensor is all-digital, which requires low design effort, and less than 1% area overhead for large benchmarks.