{"title":"设计一种用于仿真的VLSI微处理器","authors":"R. Rivin, J. Potts","doi":"10.1109/ASIC.1990.186124","DOIUrl":null,"url":null,"abstract":"The performance of high-speed digital signal processors (DSPs) poses a challenge to real-time in-circuit emulation. Because DSPs are optimized to perform arithmetic calculations in less than 50 ns, internal and external data buses can change at rates in excess of 20 million times per second. The capture and tracking of these signals and the control of the processor is the essence of real-time in-circuit emulation. In order to support high-performance emulation, these issues were emphasized during the specification and design of a DSP. The system-level requirements that drive design considerations to allow emulation of this VLSI circuit are discussed.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"695 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Designing a VLSI microprocessor for emulation\",\"authors\":\"R. Rivin, J. Potts\",\"doi\":\"10.1109/ASIC.1990.186124\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The performance of high-speed digital signal processors (DSPs) poses a challenge to real-time in-circuit emulation. Because DSPs are optimized to perform arithmetic calculations in less than 50 ns, internal and external data buses can change at rates in excess of 20 million times per second. The capture and tracking of these signals and the control of the processor is the essence of real-time in-circuit emulation. In order to support high-performance emulation, these issues were emphasized during the specification and design of a DSP. The system-level requirements that drive design considerations to allow emulation of this VLSI circuit are discussed.<<ETX>>\",\"PeriodicalId\":126693,\"journal\":{\"name\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"volume\":\"695 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1990.186124\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186124","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The performance of high-speed digital signal processors (DSPs) poses a challenge to real-time in-circuit emulation. Because DSPs are optimized to perform arithmetic calculations in less than 50 ns, internal and external data buses can change at rates in excess of 20 million times per second. The capture and tracking of these signals and the control of the processor is the essence of real-time in-circuit emulation. In order to support high-performance emulation, these issues were emphasized during the specification and design of a DSP. The system-level requirements that drive design considerations to allow emulation of this VLSI circuit are discussed.<>
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