迈向一种性价比高的硬件木马检测方法

Raymond Paseman, A. Orailoglu
{"title":"迈向一种性价比高的硬件木马检测方法","authors":"Raymond Paseman, A. Orailoglu","doi":"10.1109/VTS.2013.6548926","DOIUrl":null,"url":null,"abstract":"Due to the increasing globalization of integrated circuit fabrication, hardware security has emerged as a major issue, necessitating hardware trojan detection mechanisms. Numerous techniques exist, a subset of which we applied to 6 sets of combinational circuits and 2 sets of sequential circuits in order to effectively determine the presence of a hardware trojan. Utilizing only a single type of functional test and a single type of side-channel test, we were able to make determinations about all 6 sets of combinational circuits and 1 of the 2 sets of sequential circuits.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Towards a cost-effective hardware trojan detection methodology\",\"authors\":\"Raymond Paseman, A. Orailoglu\",\"doi\":\"10.1109/VTS.2013.6548926\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Due to the increasing globalization of integrated circuit fabrication, hardware security has emerged as a major issue, necessitating hardware trojan detection mechanisms. Numerous techniques exist, a subset of which we applied to 6 sets of combinational circuits and 2 sets of sequential circuits in order to effectively determine the presence of a hardware trojan. Utilizing only a single type of functional test and a single type of side-channel test, we were able to make determinations about all 6 sets of combinational circuits and 1 of the 2 sets of sequential circuits.\",\"PeriodicalId\":138435,\"journal\":{\"name\":\"2013 IEEE 31st VLSI Test Symposium (VTS)\",\"volume\":\"173 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-04-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE 31st VLSI Test Symposium (VTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTS.2013.6548926\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 31st VLSI Test Symposium (VTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTS.2013.6548926","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

由于集成电路制造日益全球化,硬件安全已成为一个主要问题,需要硬件木马检测机制。存在许多技术,我们将其中的一个子集应用于6组组合电路和2组顺序电路,以有效地确定硬件木马的存在。仅利用单一类型的功能测试和单一类型的侧通道测试,我们就能够确定所有6组组合电路和2组顺序电路中的1组。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Towards a cost-effective hardware trojan detection methodology
Due to the increasing globalization of integrated circuit fabrication, hardware security has emerged as a major issue, necessitating hardware trojan detection mechanisms. Numerous techniques exist, a subset of which we applied to 6 sets of combinational circuits and 2 sets of sequential circuits in order to effectively determine the presence of a hardware trojan. Utilizing only a single type of functional test and a single type of side-channel test, we were able to make determinations about all 6 sets of combinational circuits and 1 of the 2 sets of sequential circuits.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Path selection based on static timing analysis considering input necessary assignments Hot topic session 4A: Reliability analysis of complex digital systems SOC test compression scheme using sequential linear decompressors with retained free variables Contactless test access mechanism for TSV based 3D ICs Experiments and analysis to characterize logic state retention limitations in 28nm process node
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1