A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth

A 3X-oversampling hybrid clock and data recovery (CDR) circuit with programmable bandwidth has been fabricated in a 55-nm CMOS technology. The jitter tolerance analysis and the design of the proposed architecture are presented. The proposed hybrid CDR consists of a conventional phase-tracking CDR and a oversampling CDR for jitter tolerance improvement. Based on the input jitter magnitude and jitter tolerance specification requirements, different bandwidths will be selected. The measured results of jitter tolerance are 1.2 UI @ 10 MHz, 5.5 UI @ 1 MHz, and 35 UI @ 100 kHz, respectively. The total area of this design is 0.98 mm2, and the power consumption is 46.2 mW at 5-Gb/s input data rate from a 1.1V supply voltage.