创新实践环节2C:新技术，新挑战- 2

2015 IEEE 33rd VLSI Test Symposium (VTS) Pub Date : 2015-04-27 DOI:10.1109/VTS.2015.7116258

S. Sindia

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引用次数: 1

摘要

随着传统器件规模经济的变化，人们正在探索增加半导体封装中晶体管数量的替代解决方案，包括各种多芯片集成技术。这些解决方案包括3D芯片堆叠、2.5D芯片并排放在基板上、封装对封装(PoP)、系统对封装(SiP)等。特别是，2.5D和3D设备集成可能会带来新的挑战，而多芯片模块(MCM)制造中的旧挑战也会重新出现，影响新用户。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Innovative practices session 2C: New technologies, new challenges - 2

As the economics of traditional devices scaling changes, alternative solutions to increase transistor counts in semiconductor packages are being explored, including various multi-die integration techniques. These solutions include 3D die stacking, 2.5D with dies sitting side-by-side on substrate, Package-on-Package (PoP), System in Package (SiP), etc. In particular, 2.5D and 3D device integration may create new challenges and old challenges seen in multi-chip module (MCM) manufacturing also re-appear to affect new users.

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2015 IEEE 33rd VLSI Test Symposium (VTS)

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