Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Hue-Min Lin, S. Cheng, Chun-Chia Chen, F. Chiu, Kung-Sheng Lin, Chung-Bin Wu, Sling Liang, Sheng-Jen Wang, G. Chen, T. Hsiao, Chi-Hui Wang
{"title":"1.25亿像素/秒的全高清MPEG-2/H。264/VC-1视频解码器的蓝光应用程序","authors":"Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Hue-Min Lin, S. Cheng, Chun-Chia Chen, F. Chiu, Kung-Sheng Lin, Chung-Bin Wu, Sling Liang, Sheng-Jen Wang, G. Chen, T. Hsiao, Chi-Hui Wang","doi":"10.1109/ASSCC.2008.4708716","DOIUrl":null,"url":null,"abstract":"A fully-compliant high-definition video decoder LSI for Blu-ray Disc (BD) player is presented. It supports MPEC-2 MP@HL, H.264 HP@L4.1, and VC-1 AP@L3 video decoding in a single chip and features resource sharing and memory management unit to achieve area/throughput efficiency. A test chip is fabricated and integrates 515 K logic gates with 522 Kbits of embedded SRAM in 90nm single-poly seven-metal CMOS process with area of 5.06 mm2. For Blu-ray player requirements, video decoding of full 1920times1080 high-definition sequences at 60 frames per second requires 125 Mpixels/sec of processing throughput which is two times higher than comparable designs [5][6] and is achieved at 200 MHz clock frequency with power dissipation of 317 mW at 1.0 V supply voltage.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"A 125Mpixels/sec full-HD MPEG-2/H.264/VC-1 video decoder for Blu-ray applications\",\"authors\":\"Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Hue-Min Lin, S. Cheng, Chun-Chia Chen, F. Chiu, Kung-Sheng Lin, Chung-Bin Wu, Sling Liang, Sheng-Jen Wang, G. Chen, T. Hsiao, Chi-Hui Wang\",\"doi\":\"10.1109/ASSCC.2008.4708716\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully-compliant high-definition video decoder LSI for Blu-ray Disc (BD) player is presented. It supports MPEC-2 MP@HL, H.264 HP@L4.1, and VC-1 AP@L3 video decoding in a single chip and features resource sharing and memory management unit to achieve area/throughput efficiency. A test chip is fabricated and integrates 515 K logic gates with 522 Kbits of embedded SRAM in 90nm single-poly seven-metal CMOS process with area of 5.06 mm2. For Blu-ray player requirements, video decoding of full 1920times1080 high-definition sequences at 60 frames per second requires 125 Mpixels/sec of processing throughput which is two times higher than comparable designs [5][6] and is achieved at 200 MHz clock frequency with power dissipation of 317 mW at 1.0 V supply voltage.\",\"PeriodicalId\":143173,\"journal\":{\"name\":\"2008 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2008.4708716\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2008.4708716","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 125Mpixels/sec full-HD MPEG-2/H.264/VC-1 video decoder for Blu-ray applications
A fully-compliant high-definition video decoder LSI for Blu-ray Disc (BD) player is presented. It supports MPEC-2 MP@HL, H.264 HP@L4.1, and VC-1 AP@L3 video decoding in a single chip and features resource sharing and memory management unit to achieve area/throughput efficiency. A test chip is fabricated and integrates 515 K logic gates with 522 Kbits of embedded SRAM in 90nm single-poly seven-metal CMOS process with area of 5.06 mm2. For Blu-ray player requirements, video decoding of full 1920times1080 high-definition sequences at 60 frames per second requires 125 Mpixels/sec of processing throughput which is two times higher than comparable designs [5][6] and is achieved at 200 MHz clock frequency with power dissipation of 317 mW at 1.0 V supply voltage.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
