{"title":"具有pvt跟踪位线传感余量增强的高工作温度(高达300°C)低压8-T SRAM","authors":"T. T. Kim, Ngoc Le Ba","doi":"10.1109/ASSCC.2013.6691025","DOIUrl":null,"url":null,"abstract":"An 8-Kbit low power 8-T SRAM for high temperature (up to 300°C) applications is presented. Near-threshold operation is selected for minimum performance variations over a wide temperate range. We proposed a PVT-tracking bitline sensing margin enhancement technique to improve the bitline swing and the sensing window. Test chips fabricated in a commercial 1.0-μm SOI technology with high temperature interconnection option demonstrates successful SRAM operation at 2 V, 300°C. The power consumption and access time of 0.94 mW and 256ns was achieved at 2 V and 300°C.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"37 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A low voltage 8-T SRAM with PVT-tracking bitline sensing margin enhancement for high operating temperature (up to 300°C)\",\"authors\":\"T. T. Kim, Ngoc Le Ba\",\"doi\":\"10.1109/ASSCC.2013.6691025\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An 8-Kbit low power 8-T SRAM for high temperature (up to 300°C) applications is presented. Near-threshold operation is selected for minimum performance variations over a wide temperate range. We proposed a PVT-tracking bitline sensing margin enhancement technique to improve the bitline swing and the sensing window. Test chips fabricated in a commercial 1.0-μm SOI technology with high temperature interconnection option demonstrates successful SRAM operation at 2 V, 300°C. The power consumption and access time of 0.94 mW and 256ns was achieved at 2 V and 300°C.\",\"PeriodicalId\":296544,\"journal\":{\"name\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"37 2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2013.6691025\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2013.6691025","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low voltage 8-T SRAM with PVT-tracking bitline sensing margin enhancement for high operating temperature (up to 300°C)
An 8-Kbit low power 8-T SRAM for high temperature (up to 300°C) applications is presented. Near-threshold operation is selected for minimum performance variations over a wide temperate range. We proposed a PVT-tracking bitline sensing margin enhancement technique to improve the bitline swing and the sensing window. Test chips fabricated in a commercial 1.0-μm SOI technology with high temperature interconnection option demonstrates successful SRAM operation at 2 V, 300°C. The power consumption and access time of 0.94 mW and 256ns was achieved at 2 V and 300°C.