A new statistical model to extract the stress induced oxide trap number and the probability density distribution of the gate current produced by a single trap

This work presents a new model to describe the statistical properties of SILC in non-volatile memory (NVM) arrays and a procedure to extract the average number of oxide traps and the probability density of the gate leakage current induced by a single trap directly from the measured histogram of SILC. The model and the extraction procedure have been validated on SILC distributions with known parameters, generated by Monte Carlo simulations, and applied to measurements performed on FLASH memory arrays. The sensitivity of the extracted parameters on the measurement resolution is discussed in detail.