嵌入式时滞广义系统RLC电路的无源模型降阶

2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2011-12-12 DOI:10.1109/EPEPS.2011.6100232

A. Charest, M. Nakhla, R. Achar

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引用次数: 3

摘要

本文提出了一种嵌入式广义时延描述子(TDD)系统的RLC网络无源模型阶约简算法。此外，提出了一种新的TDD系统无源性验证算法。数值结果验证了所提出的算法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Passive model-order reduction of RLC circuits with embedded time-delay descriptor systems

In this paper, a new algorithm for passive model-order reduction of RLC networks with embedded general Time-Delay Descriptor (TDD) systems is presented. In addition, a new passivity verification algorithm for TDD systems is developed. Numerical results validating the proposed algorithms are also presented.

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2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems

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