基于多个计数器的测试响应压缩输出选择

Wei-Cheng Lien, Kuen-Jong Lee, K. Chakrabarty, Tong-Yu Hsieh
{"title":"基于多个计数器的测试响应压缩输出选择","authors":"Wei-Cheng Lien, Kuen-Jong Lee, K. Chakrabarty, Tong-Yu Hsieh","doi":"10.1109/VLSI-DAT.2014.6834865","DOIUrl":null,"url":null,"abstract":"Recently a novel test response compaction method called output selection is proposed to achieve high compaction ratio and high diagnosibility by observing only a subset of output response bits. In addition, this method also ensures zero aliasing and no unknown-value problem. Previously, a single counter and a multiplexer are employed as selection logic for output selection on scan-based designs. This single-counter-based approach may need to apply one pattern several times in order to observe all selection responses, hence may significantly increase the test application time. To address this weakness, this paper presents a multiple-counter-based output selection method to observe more than one output response bits at each scan-out cycle. A new response selection algorithm is developed to determine desired responses under a set of pre-defined counter operations. Results on IWLS'05 benchmarks show that compared with the single counter-based scheme, the proposed method can reduce 47.33%~67.87% test application time with only slight increase on area overhead.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Output selection for test response compaction based on multiple counters\",\"authors\":\"Wei-Cheng Lien, Kuen-Jong Lee, K. Chakrabarty, Tong-Yu Hsieh\",\"doi\":\"10.1109/VLSI-DAT.2014.6834865\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recently a novel test response compaction method called output selection is proposed to achieve high compaction ratio and high diagnosibility by observing only a subset of output response bits. In addition, this method also ensures zero aliasing and no unknown-value problem. Previously, a single counter and a multiplexer are employed as selection logic for output selection on scan-based designs. This single-counter-based approach may need to apply one pattern several times in order to observe all selection responses, hence may significantly increase the test application time. To address this weakness, this paper presents a multiple-counter-based output selection method to observe more than one output response bits at each scan-out cycle. A new response selection algorithm is developed to determine desired responses under a set of pre-defined counter operations. Results on IWLS'05 benchmarks show that compared with the single counter-based scheme, the proposed method can reduce 47.33%~67.87% test application time with only slight increase on area overhead.\",\"PeriodicalId\":267124,\"journal\":{\"name\":\"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-04-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-DAT.2014.6834865\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT.2014.6834865","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

最近提出了一种新的测试响应压缩方法,即输出选择方法,通过只观察输出响应位的一个子集来实现高压缩率和高诊断性。此外,该方法还保证了零混叠和无未知值问题。以前,在基于扫描的设计中,单个计数器和多路复用器被用作输出选择的选择逻辑。这种基于单计数器的方法可能需要多次应用一个模式来观察所有选择响应,因此可能会显著增加测试应用时间。为了解决这个缺点,本文提出了一种基于多计数器的输出选择方法,在每个扫描周期观察多个输出响应位。提出了一种新的响应选择算法,在一组预定义的计数器操作下确定期望的响应。IWLS’05基准测试结果表明,与基于单一计数器的方案相比,该方案可减少47.33%~67.87%的测试应用时间,且面积开销略有增加。
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Output selection for test response compaction based on multiple counters
Recently a novel test response compaction method called output selection is proposed to achieve high compaction ratio and high diagnosibility by observing only a subset of output response bits. In addition, this method also ensures zero aliasing and no unknown-value problem. Previously, a single counter and a multiplexer are employed as selection logic for output selection on scan-based designs. This single-counter-based approach may need to apply one pattern several times in order to observe all selection responses, hence may significantly increase the test application time. To address this weakness, this paper presents a multiple-counter-based output selection method to observe more than one output response bits at each scan-out cycle. A new response selection algorithm is developed to determine desired responses under a set of pre-defined counter operations. Results on IWLS'05 benchmarks show that compared with the single counter-based scheme, the proposed method can reduce 47.33%~67.87% test application time with only slight increase on area overhead.
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