{"title":"亚阈值偏置范围内超薄反转通道和埋道SOI mosfet的噪声特性","authors":"T. Ito, S. Sato, Y. Omura","doi":"10.1109/IMFEDK.2014.6867057","DOIUrl":null,"url":null,"abstract":"This paper considers aspects of low-frequency noise in the inversion-channel SOI nMOSFET and the buried-channel SOI pMOSFET. Analyses suggest that the inversion channel is strongly influenced by interface traps, which also weakly influence the buried-channel. It is demonstrated that such aspects are significant in the subthreshold bias range.","PeriodicalId":202416,"journal":{"name":"2014 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Characterization of noise behavior of ultrathin inversion-channel and buried-channel SOI MOSFETs in the subthreshold bias range\",\"authors\":\"T. Ito, S. Sato, Y. Omura\",\"doi\":\"10.1109/IMFEDK.2014.6867057\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper considers aspects of low-frequency noise in the inversion-channel SOI nMOSFET and the buried-channel SOI pMOSFET. Analyses suggest that the inversion channel is strongly influenced by interface traps, which also weakly influence the buried-channel. It is demonstrated that such aspects are significant in the subthreshold bias range.\",\"PeriodicalId\":202416,\"journal\":{\"name\":\"2014 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK)\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-06-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMFEDK.2014.6867057\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMFEDK.2014.6867057","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Characterization of noise behavior of ultrathin inversion-channel and buried-channel SOI MOSFETs in the subthreshold bias range
This paper considers aspects of low-frequency noise in the inversion-channel SOI nMOSFET and the buried-channel SOI pMOSFET. Analyses suggest that the inversion channel is strongly influenced by interface traps, which also weakly influence the buried-channel. It is demonstrated that such aspects are significant in the subthreshold bias range.