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2014 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK)最新文献

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Germanium diode modeling for sound effect circuit design 声效电路设计中的锗二极管建模
Pub Date : 2014-06-19 DOI: 10.1109/IMFEDK.2014.6867059
Hirokazu Oda, A. Hiroki, Takaaki Sano, Takaya Oyama
This paper describes a germanium diode model for sound effect circuit design. The parameters of the diode model have been investigated by comparing with experimental data. In lower voltage regions, the parameters of the SPICE library have been compared with experimental current voltage characteristics. A diode model with accurate parameters has been proposed. The diode model has been implemented into a circuit simulator. Output waveforms of a distortion circuit have been investigated by comparing with experimental data. It is found that the modeling of the diode in low voltage region is essential in simulating for the distortion circuits.
本文介绍了一种用于声效电路设计的锗二极管模型。通过与实验数据的比较,对二极管模型的参数进行了研究。在较低电压区域,SPICE库的参数与实验电流电压特性进行了比较。提出了一种具有精确参数的二极管模型。该二极管模型已在电路模拟器中实现。通过与实验数据的比较,研究了一种畸变电路的输出波形。研究发现,在畸变电路的仿真中,低压区二极管的建模是必不可少的。
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引用次数: 0
Macromodeling of operational amplifiers for sound effect circuit design 运放声效电路设计的宏建模
Pub Date : 2014-06-19 DOI: 10.1109/IMFEDK.2014.6867058
Takaya Oyama, A. Hiroki, Takaaki Sano
This paper describes a macromodeling of operational amplifiers for sound effect circuit design. The modular macromodel of operational amplifiers has been investigated for distortion circuits. The macromodel includes the voltage limiting stage with accurate power supply voltages. The macromodel has been implemented in a circuit simulator and the output voltages are compared with experimental data for a distortion circuit. It is found that the modeling of operational amplifiers with accurate power supply voltages is essential in simulating the output wave.
本文介绍了一种用于运放音响电路设计的宏观建模方法。对运算放大器的模块化宏模型进行了研究。宏观模型包括具有精确电源电压的限压阶段。在电路模拟器中实现了该宏模型,并将输出电压与一个畸变电路的实验数据进行了比较。研究发现,精确供电电压的运算放大器的建模是模拟输出波的关键。
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引用次数: 2
Multiple-input NAND cirucit using polycrystalline silicon thin-film transistors and set-reset flip-flop circuit using the NAND circuits 使用多晶硅薄膜晶体管的多输入NAND电路和使用NAND电路的设置复位触发器电路
Pub Date : 2014-06-19 DOI: 10.1109/IMFEDK.2014.6867075
Y. Nagase, T. Matsuda, M. Kimura, Taketoshi Matsumoto, H. Kobayashi
We have evaluated multiple-input NAND circuits using polycrystalline silicon thin-film transistors and found that the output pulse became degraded for the 3-input NAND circuit. Moreover, we have fabricated a set-reset flip-flop (SR-FF) circuit using the 2-input NAND circuits and confirmed that the SR-FF circuit operated correctly.
我们评估了使用多晶硅薄膜晶体管的多输入NAND电路,发现3输入NAND电路的输出脉冲变得退化。此外,我们使用2输入NAND电路制作了一个设置复位触发器(SR-FF)电路,并确认SR-FF电路正常工作。
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引用次数: 0
Output voltage stability of SPMC Type AC-AC converter for power management in IT system IT系统电源管理用SPMC型交流变换器的输出电压稳定性
Pub Date : 2014-06-19 DOI: 10.1109/IMFEDK.2014.6867096
Hiroaki Ohtsuka, M. Muraguchi, Yitao Ma, T. Endoh
This paper focuses on the analyses of output stability of Single-Phase-Matrix-Converter (SPMC) type AC-AC converter for power management in the IT system. The SPMC employing power MOS devices is studied to contribute to the efficiency improvement and stabilization of AC-DC power supply circuit in IT systems. In detail, the output voltage dependency of SPMC is evaluated with triangular wave control signal with the amplitude range from 5V to 20V and the frequency range from 1kHz to 2MHz.
本文重点分析了IT系统中用于电源管理的单相矩阵变换器(SPMC)型交流变换器的输出稳定性。为了提高IT系统中交直流供电电路的效率和稳定性,研究了采用功率MOS器件的SPMC。在5V ~ 20V、1kHz ~ 2MHz的三角波控制信号下,对SPMC的输出电压依赖性进行了评估。
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引用次数: 1
Correlation between BTI-induced degradations and process variations by measuring frequency of ROs 通过测量活性氧的频率,bti诱导的降解与过程变化之间的相关性
Pub Date : 2014-06-19 DOI: 10.1109/IMFEDK.2014.6867095
M. Yabuuchi, Ryo Kishida, Kazutoshi Kobayashi
We analyze the correlation between BTI (Bias Temperature Instability)-induced degradations and process variations. BTI shows a strong effect on highly scaled LSIs in the same way as the process variations. It is necessary to predict the combinational effects. We should analyze both aging-degradations and process variations of MOSFETs to explain the correlation. We measure initial frequencies and the aging-degradations of ROs (ring oscillators) of 65-nm process test circuits. The initial frequencies of ROs follow gaussian distributions. The degradations can be approximated by logarithmic function of stress time. The degradation at the “fast” condition of the variations has a higher impact on the frequency than the “slow” one. The correlation coefficient is 0.338. In this case, we can reduce the design margin for BTI-induced degradations because the degradation at the “slow” conditon on the variations is smaller than the average.
我们分析了BTI(偏置温度不稳定性)引起的退化和工艺变化之间的相关性。与工艺变化一样,BTI对高尺度lsi也有很强的影响。有必要对其组合效应进行预测。我们应该分析mosfet的老化退化和工艺变化来解释相关性。我们测量了65纳米工艺测试电路的初始频率和ROs(环形振荡器)的老化退化。ROs的初始频率服从高斯分布。这种退化可以用应力时间的对数函数来近似表示。变化的“快”条件下的退化比“慢”条件下的退化对频率的影响更大。相关系数为0.338。在这种情况下,我们可以减少bti引起的退化的设计余量,因为在“缓慢”条件下,变化的退化小于平均值。
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引用次数: 4
Maximum and minimum voltage sample and hold circuits employing operational amplifiers composed of polycrystalline silicon thin-film transistors 采用由多晶硅薄膜晶体管组成的运算放大器的最大和最小电压采样和保持电路
Pub Date : 2014-06-19 DOI: 10.1109/IMFEDK.2014.6867076
Y. Ohno, Yoshihiro Ito, Y. Nagase, Akito Yoshikawa, T. Matsuda, M. Kimura
We have developed maximum and minimum voltage sample and hold circuits employing operational amplifiers (OPAMPs) composed of polycrystalline silicon (poly-Si) thin-film transistors (TFTs). It was confirmed that the maximum and minimum voltages are successfully sampled and held. It was also confirmed that the restoring ratio has a peak near a certain value of the operation frequency. We would like you to propose novel applications using these circuits.
我们开发了使用由多晶硅(poly-Si)薄膜晶体管(TFTs)组成的运算放大器(opamp)的最大和最小电压采样和保持电路。结果表明,最大和最小电压被成功采样并保持。还证实了恢复比在工作频率的某一值附近有一个峰值。我们希望你能提出使用这些电路的新应用。
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引用次数: 3
Micro systems for sustainable society 可持续社会的微系统
Pub Date : 2014-06-19 DOI: 10.1109/IMFEDK.2014.6867043
M. Esashi
Wafer level adhesive bonding has been applied for the fabrication of micro systems which have heterogeneous components on LSI. Devices formed on a carrier wafer are transferred on a LSI wafer, which makes versatile heterogeneous integration possible. This has been applied to resonator, piezoelectric switch, tactile sensor, electron source and other value-added devices.
晶圆级粘接技术已被应用于制造具有异质元件的微系统。在载流子晶圆上形成的器件被转移到LSI晶圆上,这使得通用异构集成成为可能。已应用于谐振器、压电开关、触觉传感器、电子源等增值器件。
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引用次数: 0
Spectroscopic electrical characterization of post-resistive-transition SiO2 films 后电阻跃迁SiO2薄膜的光谱电学特性
Pub Date : 2014-06-19 DOI: 10.1109/IMFEDK.2014.6867074
R. Yamaguchi, S. Sato, Y. Omura, K. Nakamura
This paper demonstrates the electronic structures of SiO2 films in low-resistance state and high-resistance state. The electronic structure is also characterized spectroscopically by means of the current fluctuation.
研究了SiO2薄膜在低阻和高阻状态下的电子结构。电子结构也通过电流波动进行光谱表征。
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引用次数: 1
Estimation of threshold voltage from frequency of ring oscillator 从环形振荡器的频率估计阈值电压
Pub Date : 2014-06-19 DOI: 10.1109/IMFEDK.2014.6867084
Takuya Matsumoto, H. Makino, T. Yoshimura, S. Iwade, Y. Matsuda
This paper proposes the estimation method of the threshold voltage (Vth) of the transistor from the frequency of the ring oscillator (RO) without analog measurement. Two distributions of delays, in which the contour lines are nearly orthogonal with each other, are derived from the measured frequencies of three kinds of ROs. The Vth can easily be calculated from the two distributions by fitting to the quadratic function and using the `goal-seek' function of Excel. The accuracy of the calculated Vth is evaluated for various conditions. By optimizing the condition and dividing the fitting range, the error decreases down to 5mv which is sufficient for an accurate estimation.
本文提出了一种无需模拟测量,仅从环形振荡器(RO)的频率估计晶体管阈值电压(Vth)的方法。从三种ROs的测量频率出发,导出了等高线几乎正交的两种时延分布。通过拟合二次函数和使用Excel的“目标寻求”函数,可以很容易地从两个分布中计算出第v个。计算出的Vth的精度在各种条件下进行了评估。通过优化条件和划分拟合范围,误差减小到5mv,足以进行准确估计。
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引用次数: 1
Schottky barrier height reduction of NiGe/Ge junction by P ion implantation for metal source/drain Ge CMOS devices P离子注入对金属源极/漏极Ge CMOS器件中nge /Ge结肖特基势垒高度的降低
Pub Date : 2014-06-19 DOI: 10.1109/IMFEDK.2014.6867050
H. Oka, Y. Minoura, T. Hosoi, T. Shimura, Heiji Watanabe
We have demonstrated effective electron Schottky barrier height (eSBH) reduction of NiGe/Ge contacts using phosphorus ion implantation after germanidation. The eSBH was drastically reduced from 0.62 eV to 0.09 eV under optimum implantation and subsequent annealing conditions. Moreover, systematic studies of NiGe/Ge contacts with various P ion profiles indicated the variation in the eSBH at NiGe/Ge interface. This method allows us to design and control junction characteristics for future Ge-based devices.
我们证明了在锗化后使用磷离子注入可以有效地降低锗锗接触的电子肖特基势垒高度。在最佳注入和后续退火条件下,eSBH从0.62 eV大幅降低到0.09 eV。此外,系统地研究了不同P离子谱的NiGe/Ge接触,表明了NiGe/Ge界面eSBH的变化。这种方法使我们能够设计和控制未来基于ge的器件的结特性。
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引用次数: 1
期刊
2014 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK)
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