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引用次数: 2
摘要
本文介绍了一种采用280GHz fT 0.7um InP HBT技术的12bit 10GSps电流转向数模转换器(DAC)。DAC核心以双采样方式工作，从而将最大时钟频率降低一半。双采样开关被分离，以减少符号间的干扰。采用改进的电流转向开关结构，提高了高频动态性能。仿真结果表明，该芯片的DNL/INL分别为0.7/0.8 LSB。低频时的SFDR在71dBc以上，奈奎斯特频率以下的最低SFDR在46.96dBc以上。
A 12-bit 10GSps ultra high speed DAC in InP HBT technology
In this paper a 12bit 10GSps current-steering digital-to-analog converter (DAC) in 280GHz fT 0.7um InP HBT technology is presented. The DAC core works in a double-sampling way, which reduces the maximum clock frequency by half. The double-sampling switch is separated to reduce the inter-symbol-interference. An improved current steer switch architecture is adopted to enhance high frequency dynamic performance. According to the simulation results, the chip achieved a DNL/INL of 0.7/0.8 LSB respectively. The SFDR at low frequency is above 71dBc, and the lowest SFDR up to Nyquist frequency is above 46.96dBc.
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