基于130nm BiCMOS技术的60 GHz数字可调全集成双基地干涉雷达收发器

M. Voelkel, M. Dietz, A. Hagelauer, E. M. Hussein, D. Kissinger, R. Weigel
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引用次数: 1

摘要

本文介绍了一种用于高精度测量的60 GHz单片双基地干涉雷达收发器。该集成收发器采用IHP公司(SG13G2)的0.13 μm SiGe BiCMOS工艺设计,包括LNA、无源六端口结构、检测器、乘频器、多路复用器、功率放大器和数字接口。该芯片的尺寸为2330 μm x 1360 μm,在3.3 V电源下,最大功耗为533mw。电路提供7.5 GHz和15ghz两个频率输入,在最小输入功率为- 20dbm的情况下,将两个频率输入相乘到60ghz。该芯片在61 GHz时的最大输出功率为9 dBm。输入路径可选,输出功率可通过数字接口在-23和9dbm之间调节,工作频率为60ghz。此外,六端口的参考输入功率和射频输入功率可以在13.2 dB的范围内调节。最小输入参考P1dB为-24.1 dBm。使用多路复用器,接收器参考可以与发射器分离,从而允许两者相互独立地使用。串行接口采用0.13 μm CMOS逻辑实现,由20位移位寄存器、解码器和模拟接口组成。
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A Digital Adjustable Fully Integrated Bistatic Interferometric Radar Transceiver at 60 GHz in a 130 nm BiCMOS Technology
In this paper a 60 GHz monolithic bistatic interferometric radar transceiver for high precision measuring is presented. The integrated transceiver has been designed using a 0.13 μm SiGe BiCMOS process from IHP (SG13G2) and includes a LNA, a passive six-port structure, detectors, multiplier, multiplexer, power amplifier and a digital interface. The chip has a size of 2330 μm x 1360 μm and a maximum power consumption of 533 mW from a 3.3 V power supply. The circuit provides two frequency inputs of 7.5 and 15 GHz and multiplies them up to 60 GHz at a minimum input power of -20 dBm. The chip delivers a maximum output power of 9 dBm at 61 GHz. The input path is selectable and the output power is adjustable by a digital interface between -23 and 9 dBm at 60 GHz. Also the reference input power of the six-port and the RF input power can be adjusted in a range of 13.2 dB. The minimum input referred P1dB is -24.1 dBm. With a multiplexer, the receiver reference can be separated from the transmitter, which allows the use of both independently from each other. The serial interface is realized in 0.13 μm CMOS logic and consists of a 20 bit shift register, decoder and an analog interface.
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