M. Seo, A. Young, M. Urteaga, Z. Griffith, M. Rodwell, M. Choe, M. Field
{"title":"一个220-225.9 GHz InP HBT单片锁相环","authors":"M. Seo, A. Young, M. Urteaga, Z. Griffith, M. Rodwell, M. Choe, M. Field","doi":"10.1109/CSICS.2011.6062495","DOIUrl":null,"url":null,"abstract":"We present a 220 GHz fundamental PLL, based on a 220 GHz VCO, 2:1 dynamic frequency divider, fifth-order sub-harmonic phase detector, active loop filter, and output amplifier, fabricated in an InP HBT technology. The measured PLL locking range was 220.0 to 225.9 GHz, with -83 dBc/Hz of phase noise at a 100 KHz offset, while consuming 465.3 mW. The PLL occupies 1.1 mm2 including pads.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 220-225.9 GHz InP HBT Single-Chip PLL\",\"authors\":\"M. Seo, A. Young, M. Urteaga, Z. Griffith, M. Rodwell, M. Choe, M. Field\",\"doi\":\"10.1109/CSICS.2011.6062495\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a 220 GHz fundamental PLL, based on a 220 GHz VCO, 2:1 dynamic frequency divider, fifth-order sub-harmonic phase detector, active loop filter, and output amplifier, fabricated in an InP HBT technology. The measured PLL locking range was 220.0 to 225.9 GHz, with -83 dBc/Hz of phase noise at a 100 KHz offset, while consuming 465.3 mW. The PLL occupies 1.1 mm2 including pads.\",\"PeriodicalId\":275064,\"journal\":{\"name\":\"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSICS.2011.6062495\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2011.6062495","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We present a 220 GHz fundamental PLL, based on a 220 GHz VCO, 2:1 dynamic frequency divider, fifth-order sub-harmonic phase detector, active loop filter, and output amplifier, fabricated in an InP HBT technology. The measured PLL locking range was 220.0 to 225.9 GHz, with -83 dBc/Hz of phase noise at a 100 KHz offset, while consuming 465.3 mW. The PLL occupies 1.1 mm2 including pads.
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