{"title":"一个CMOS四元到二进制的逻辑解码器","authors":"Jeong Beom Kim","doi":"10.1109/ICSICT.2008.4734924","DOIUrl":null,"url":null,"abstract":"This paper proposes a quaternary-to-binary logic decoder using current-mode multiple-valued logic (MVL) CMOS circuits. The circuit is achieved a device reduction of 23.5%, an interconnection reduction of 25.0%, and a power-delay-product reduction of 43.1%. Therefore, this circuit is superior to the previous circuit in both the circuit occupied area and the reliability. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25 um standard CMOS technology with the supply voltage 2.5 V.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A CMOS quaternary-to-binary logic decoder\",\"authors\":\"Jeong Beom Kim\",\"doi\":\"10.1109/ICSICT.2008.4734924\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a quaternary-to-binary logic decoder using current-mode multiple-valued logic (MVL) CMOS circuits. The circuit is achieved a device reduction of 23.5%, an interconnection reduction of 25.0%, and a power-delay-product reduction of 43.1%. Therefore, this circuit is superior to the previous circuit in both the circuit occupied area and the reliability. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25 um standard CMOS technology with the supply voltage 2.5 V.\",\"PeriodicalId\":436457,\"journal\":{\"name\":\"2008 9th International Conference on Solid-State and Integrated-Circuit Technology\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 9th International Conference on Solid-State and Integrated-Circuit Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.2008.4734924\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.2008.4734924","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper proposes a quaternary-to-binary logic decoder using current-mode multiple-valued logic (MVL) CMOS circuits. The circuit is achieved a device reduction of 23.5%, an interconnection reduction of 25.0%, and a power-delay-product reduction of 43.1%. Therefore, this circuit is superior to the previous circuit in both the circuit occupied area and the reliability. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25 um standard CMOS technology with the supply voltage 2.5 V.
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