采用片上抖动测试电路进行锁相环自校准

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2006-12-19 DOI:10.1109/DFT.2006.26

T. Xia, S. Wyatt, Rupert Ho

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引用次数: 1

摘要

本文实现了一种新的自适应锁相环。该锁相环采用简单而有效的抖动测试电路来监测锁相环的抖动性能。此外，它还使用数字控制单元来动态调整开关环路滤波器以抑制抖动。通过使用这种结构，锁相环锁定速度和抖动性能之间的权衡可以得到平衡

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration

In this paper, a new adaptive PLL is implemented. This PLL employs a simple yet effective jitter test circuit to monitor the PLL jitter performance. Additionally, it uses a digital control unit to dynamically adjust the switched loop filter to suppress the jitter. By using this structure, the trade-off between the PLL locking speed and jitter performance can be balanced

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2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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