4gb /s ECL栅极母片

M. Tamamura, S. Emori, Yoshio Watanabe, Isao Shimotsuhama, N. Kikuchi, W. Ishibashi, K. Tachibana
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引用次数: 2

摘要

作者提出了一种新颖的半定制集成电路,称为门母片,它可以为高比特率信号获得清晰的眼纹。栅极母片的主要设计特点是:先进的硅双极工艺,芯片结构减少信号干扰而不是增加栅极密度,内部连接仅使用第二层金属层
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4 Gb/s ECL gate masterslice
The authors present a novel semicustom IC called the gate masterslice, which enables a clear eye pattern to be obtained for high-bit-rate signals. Key design features of the gate masterslice are: an advanced Si bipolar process, chip structure that reduces signal interference rather than increasing gate density, and internal connection using only the second metal layer
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A 1.4 ns/64 kb RAM with 85 ps/3680 logic gate array A gate matrix deformation and three-dimensional maze routing for dense MOS module generation A submicron CMOS triple level metal technology for ASIC applications Hot carrier effects on CMOS circuit performance The QML-an approach for qualifying ASICs
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