Novel measurement technique for trapped charge centroid in gate insulator (of DRAM)

A measurement technique was developed that makes it possible to estimate both trap charges and the center of the trap-charge distribution, the so-called charge centroid. This technique is applicable to the study of trap/detrap characteristics of injected charges in the gate insulator film of a stacked capacitor with a heavily doped polysilicon/insulator/heavily doped polysilicon structure. C-V characteristics for the stacked capacitor are modeled by using depletion layers in both polysilicon electrodes. Experimental fitting of the model to C-V data was carried out and trap charges and the charge centroid were obtained. Using this technique, trap/detrap characteristics for nanometer-think ONO film were investigated, and the deterioration in DRAM (dynamic random-access memory) cell signal voltage for a stacked capacitor cell, due to detrapping the trap charges, is discussed.<>