用于颜色矩阵和卷积的流水线专用集成电路

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186140

K. Hsu, L. D'Luna, H. Yeh, W.A. Cook, G.W. Brown

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引用次数: 4

摘要

讨论了一种可以进行3*3矩阵乘法和3*3数字卷积的VLSI芯片。内置自检(BIST)技术已纳入芯片，以确保高故障覆盖率。该芯片采用2 μ m CMOS技术，采用硅编译器进行物理布局。该设备的设计工作频率为14.3 MHz，适用于实时视频和图像处理应用。

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A pipelined ASIC for color matrixing and convolution

A VLSI chip that can perform either 3*3 matrix multiplication or 3*3 digital convolution is discussed. Built-in self-test (BIST) techniques have been incorporated into the chip to ensure high fault coverage. The chip is designed in a 2- mu m CMOS technology using a silicon compiler for physical layout. The device is designed to operate at 14.3 MHz, making it suitable for real-time video and image processing applications.<>

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

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