具有降低峰值电流噪声的实验性16Mb DRAM

Daeje Chin, Changhyun Kim, Y. Choi, D. Min, H. Hwang, Hoon Choi, S. Cho, T. Chung, C. Park, Y. Shin, Kwangpyuk Suh, Y. E. Park
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引用次数: 8

摘要

在高密度DRAM中,在传统方案中,当感测放大器开始锁存时,通常会产生200-300mA的峰值电流(图a),导致无法忍受的电源总线噪声。四相驱动的PMOS恢复是通过连续触发4个上拉晶体管来减小电流。[1]然而,NMOS锁存器的初始传感操作对信号裕度和传感速度更为关键。
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An expermental 16Mb DRAM with reduced peak-current noise
In high-density DRAM'S, a large peak current of typically 200-300mA occurs when sense amplifiers start latching in a conventional scheme (Figure la), resulting in intolerable power bus noise. Four-phase drive for PMOS restoring was reported to reduce the pe& current by triggering four pull-up transistors successively.[l] The initial sensing operation by NMOS latches, however, is more critical to signal margjn and sensing speed.
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