带VSS发生器的快速访问BiCMOS SRAM架构

Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI:10.1109/VLSIC.1990.111087

T. Douseki, Y. Ohmori, H. Yoshino, J. Yamada

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引用次数: 15

摘要

提出了一种快速存取的中间电源电压级BiCMOS SRAM (ISVOL)架构，利用低亚微米mosfet将电路技术提升到兆位级SRAM。为了验证这一概念的有效性，评估和报告了一个256 kb的SRAM，典型的访问时间为5 ns。供电电压与接入时间的关系如图所示。这种结构可以在电源电压变化15%的情况下将接入时间方差抑制在4%以内

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Fast-access BiCMOS SRAM architecture with a VSS generator

A fast-access intermediate supply voltage level BiCMOS SRAM (ISVOL) architecture is proposed for advancing circuit technology to megabit-level SRAMs using low-submicron MOSFETs. To verify this concept's effectiveness, a 256-kb SRAM, with a typical access time of 5 ns, is evaluated and reported. The access time dependence of the supply voltage is shown. This architecture can suppress the access time variance to within 4% for a 15% supply voltage variation

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Digest of Technical Papers., 1990 Symposium on VLSI Circuits

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