TSV etching and VDP process integration for high reliability

TSV (Thru Silicon Via) application for 2.5D silicon interposers and 3D stacked devices is expected to realize a next-generation semiconductor device with high packaging density, power saving, and high-speed signal transmission, etc. Recently, discussions on long-term reliability of TSV has been triggered, the establishment of TSV integration technologies contribute to reliability is strongly requested to enable TSV packaging promote mass production. Compared with Bosch etching method, relatively smooth sidewall could be obtained in TSV fabrication by using scallop-free etching method. In scallop-free TSV, there is possibility that TSV reliability can progress due to the thermal-mechanical stress-relief of heterogeneous stacked layer in TSVs, and the continuous PVD barrier metal layer relatively easily obtained on the smooth sidewall of TSV. However, TSV reliability is not decided by only etching method. For example, the wiring-delay by the dielectric constants of the liner film is an important problem which is referred to both case of scallop existence and scallop-free. SiO2 film is adopted generally in TSVs, but is fatal to the high frequency device of the GHz band. Therefore, kind of polymer film is introduced as a low dielectric constant for a high frequency band. And also, the film stress is quite small. This suggests the anti-stress high tolerance capability on the thin wafer. Not depended on scallop-free etching method only, the use of polymer film will contribute to more reliable TSV integration from the perspective of liner material.