A. Subirats, A. Arreghini, R. Delhougne, E. Rosseel, A. Hikavyy, L. Breuil, S. V. Palayam, G. Van den bosch, D. Linten, A. Furnémont
{"title":"Trap Reduction and Performances Improvements Study after High Pressure Anneal Process on Single Crystal Channel 3D NAND Devices","authors":"A. Subirats, A. Arreghini, R. Delhougne, E. Rosseel, A. Hikavyy, L. Breuil, S. V. Palayam, G. Van den bosch, D. Linten, A. Furnémont","doi":"10.1109/IEDM.2018.8614667","DOIUrl":null,"url":null,"abstract":"We study the impact of HPAP on SCC 3D NAND devices. We show that the process can reduce trap density but is leaving trap impact on devices VT unaffected. It is also shown, both by simulations and measurements, that further scaling could lead to the increase of single trap impact. Finally, we measure that despite largely improving devices electrical parameter, HPAP has no effect on memory performances (Program/Erase) or could slightly degrade it (Retention).","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2018.8614667","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
摘要
我们研究了HPAP对SCC 3D NAND器件的影响。我们表明该工艺可以降低陷阱密度，但陷阱对器件VT的影响不受影响。模拟和测量结果也表明，进一步的缩放可能导致单阱影响的增加。最后，我们测量到，尽管在很大程度上改善了设备的电气参数，但HPAP对内存性能(程序/擦除)没有影响，或者可能会略微降低内存性能(保留)。
Trap Reduction and Performances Improvements Study after High Pressure Anneal Process on Single Crystal Channel 3D NAND Devices
We study the impact of HPAP on SCC 3D NAND devices. We show that the process can reduce trap density but is leaving trap impact on devices VT unaffected. It is also shown, both by simulations and measurements, that further scaling could lead to the increase of single trap impact. Finally, we measure that despite largely improving devices electrical parameter, HPAP has no effect on memory performances (Program/Erase) or could slightly degrade it (Retention).
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
