最后通道背控铁电晶体管的高速存储器操作

2020 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2020-12-12 DOI:10.1109/IEDM13553.2020.9371940

Abhishek A. Sharma, B. Doyle, H. Yoo, I. Tung, J. Kavalieros, M. Metz, M. Reshotko, P. Majhi, Tobias L. Brown-Heft, Yu-Jin Chen, V. Le

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引用次数: 29

摘要

采用通道末端工艺流程制备了背门控结构的尺度铁电晶体管(Lg =76 nm)。利用这种方法，优化的铁电栅氧化膜可以与半导体沟道解耦，以减少寄生界面。结果表明，在1.8 V电压下，具有3σ存储窗口的铁电晶体管可实现10 ns的快速编程时间(包括瞬时读后写)和1012个周期的高寿命。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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High Speed Memory Operation in Channel-Last, Back-gated Ferroelectric Transistors

Scaled ferroelectric transistors (Lg =76 nm) in a back- gated configuration are fabricated with a channel-last process flow. Using this approach, optimization of the ferroelectric gate oxide film can be decoupled from that of the semiconductor channel to reduce parasitic interfaces. As a result, ferroelectric transistors with 3σ memory window for fast programming time of 10 ns (including an instantaneous read-after-write) at 1.8 V and high endurance of 1012 cycles are demonstrated for the first time.

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2020 IEEE International Electron Devices Meeting (IEDM)

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