条件加法器高效性能驱动生成器的实现

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI:10.1109/EURDAC.1993.410668

B. Becker, R. Drechsler, P. Molitor

{"title":"条件加法器高效性能驱动生成器的实现","authors":"B. Becker, R. Drechsler, P. Molitor","doi":"10.1109/EURDAC.1993.410668","DOIUrl":null,"url":null,"abstract":"The authors present data structures and an efficient algorithm realizing efficient performance driven generation of integer adders. The generator is parameterized in n, the operands' bitlength, and t/sub n/, the delay of the addition. It outputs an area minimal n-bit adder of the conditional-sum type with delay /spl les/t/sub n/, if such a circuit exists.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"On the implementation of an efficient performance driven generator for conditional-sum-adders\",\"authors\":\"B. Becker, R. Drechsler, P. Molitor\",\"doi\":\"10.1109/EURDAC.1993.410668\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors present data structures and an efficient algorithm realizing efficient performance driven generation of integer adders. The generator is parameterized in n, the operands' bitlength, and t/sub n/, the delay of the addition. It outputs an area minimal n-bit adder of the conditional-sum type with delay /spl les/t/sub n/, if such a circuit exists.<<ETX>>\",\"PeriodicalId\":339176,\"journal\":{\"name\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-09-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EURDAC.1993.410668\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1993.410668","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

作者提出了数据结构和一种高效的算法，实现了高效的性能驱动的整数加法器生成。生成器的参数是n(操作数的位长)和t/sub n/(加法的延迟)。如果存在这样的电路，则输出具有延迟/spl /t/sub / n/的条件和类型的面积最小n位加法器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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On the implementation of an efficient performance driven generator for conditional-sum-adders

The authors present data structures and an efficient algorithm realizing efficient performance driven generation of integer adders. The generator is parameterized in n, the operands' bitlength, and t/sub n/, the delay of the addition. It outputs an area minimal n-bit adder of the conditional-sum type with delay /spl les/t/sub n/, if such a circuit exists.<>

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Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

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