{"title":"脉冲宽度控制PLL/DLL使用软温度计代码","authors":"T. Nakura, K. Asada","doi":"10.1109/ASSCC.2013.6691053","DOIUrl":null,"url":null,"abstract":"This paper demonstrates pulse width controlled PLL and DLL using a soft thermometer code. The oscillation frequency control in the PLL and the delay control in the DLL are conducted by a mostly digital with one bit analog code. Both of our PLL/DLL do not use an area-consuming capacitor, resulting in small silicon area implementation. A 65nm CMOS process uses only 120μm×30μm area for the PLL+DLL. They realized 2.80GHz operation consuming 1.35mW/4.65mW with 1.60ps/1.78ps rms jitter from the PLL/DLL output signals.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Pulse width controlled PLL/DLL using soft thermometer code\",\"authors\":\"T. Nakura, K. Asada\",\"doi\":\"10.1109/ASSCC.2013.6691053\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper demonstrates pulse width controlled PLL and DLL using a soft thermometer code. The oscillation frequency control in the PLL and the delay control in the DLL are conducted by a mostly digital with one bit analog code. Both of our PLL/DLL do not use an area-consuming capacitor, resulting in small silicon area implementation. A 65nm CMOS process uses only 120μm×30μm area for the PLL+DLL. They realized 2.80GHz operation consuming 1.35mW/4.65mW with 1.60ps/1.78ps rms jitter from the PLL/DLL output signals.\",\"PeriodicalId\":296544,\"journal\":{\"name\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2013.6691053\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2013.6691053","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Pulse width controlled PLL/DLL using soft thermometer code
This paper demonstrates pulse width controlled PLL and DLL using a soft thermometer code. The oscillation frequency control in the PLL and the delay control in the DLL are conducted by a mostly digital with one bit analog code. Both of our PLL/DLL do not use an area-consuming capacitor, resulting in small silicon area implementation. A 65nm CMOS process uses only 120μm×30μm area for the PLL+DLL. They realized 2.80GHz operation consuming 1.35mW/4.65mW with 1.60ps/1.78ps rms jitter from the PLL/DLL output signals.