K. Madhu, Tarun Singla, S. Nandy, R. Narayan, Francois Neumann, P. Baufreton
{"title":"REDEFINE®™:用于实时应用的wcet友好硬件加速器案例(正在开发中)","authors":"K. Madhu, Tarun Singla, S. Nandy, R. Narayan, Francois Neumann, P. Baufreton","doi":"10.1145/3125501.3125526","DOIUrl":null,"url":null,"abstract":"REDEFINE is a distributed dynamic dataflow architecture, designed for exploiting parallelism at various granularities as an embedded system-on-chip (SoC). This paper dwells on the flexibility of REDEFINE architecture and its execution model in accelerating real-time applications coupled with a WCET analyzer that computes execution time bounds of real time applications.","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"REDEFINE®™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress)\",\"authors\":\"K. Madhu, Tarun Singla, S. Nandy, R. Narayan, Francois Neumann, P. Baufreton\",\"doi\":\"10.1145/3125501.3125526\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"REDEFINE is a distributed dynamic dataflow architecture, designed for exploiting parallelism at various granularities as an embedded system-on-chip (SoC). This paper dwells on the flexibility of REDEFINE architecture and its execution model in accelerating real-time applications coupled with a WCET analyzer that computes execution time bounds of real time applications.\",\"PeriodicalId\":259093,\"journal\":{\"name\":\"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/3125501.3125526\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3125501.3125526","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
REDEFINE®™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress)
REDEFINE is a distributed dynamic dataflow architecture, designed for exploiting parallelism at various granularities as an embedded system-on-chip (SoC). This paper dwells on the flexibility of REDEFINE architecture and its execution model in accelerating real-time applications coupled with a WCET analyzer that computes execution time bounds of real time applications.
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