用于高性能75nm栅长pmosfet的硅化硅侧壁源极和漏极(S/sup /D)结构

T. Yoshitomi, M. Saito, T. Ohguro, M. Ono, H. Momose, H. Iwai
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引用次数: 17

摘要

针对小于0.1 /spl mu/m栅极长度的p- mosfet,提出了硅化硅-侧壁源漏(S/sup 4/D)结构,该结构可以实现极小的源漏串联电阻和极小的短沟道效应。利用该结构制备了75 mm栅极长度的p- mosfet,并获得了良好的电特性。本实验只制备了p- mosfet,但S/sup 4/D结构也适用于低于0.1 /spl mu/m栅极长度的CMOS器件,因为基本上,侧壁非晶硅不需要预先原位掺杂,就可以通过源极和漏极注入容易掺杂源极和漏极掺杂。
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Silicided silicon-sidewall source and drain (S/sup 4/D) structure for high-performance 75-nm gate length pMOSFETs
Silicided Silicon-Sidewall Source and Drain (S/sup 4/D) structures were proposed for sub-0.1 /spl mu/m gate length p-MOSFETs as the structure which can realize extremely small source and drain series resistance with small short-channel effects. By using this structure, 75 mm gate length p-MOSFETs were fabricated and very good electrical characteristics were confirmed. In this experiment, only p-MOSFETs were fabricated, but the S/sup 4/D structures are also suitable for the sub-0.1 /spl mu/m gate length CMOS devices, because, basically, the sidewall amorphous silicon is easily doped with the dopant of source and drain by source and drain implantation without prior in situ doping.
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