采用GaAs伪晶HEMT的30 GHz 2级MMIC低噪声放大器

A. Rasmi, I. M. Azmi, A. Rahim, H. Hsu, E. Chang
{"title":"采用GaAs伪晶HEMT的30 GHz 2级MMIC低噪声放大器","authors":"A. Rasmi, I. M. Azmi, A. Rahim, H. Hsu, E. Chang","doi":"10.1109/EDSSC.2013.6628044","DOIUrl":null,"url":null,"abstract":"Summary form only given. This paper presents the design and simulated performance of millimeter-wave monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA). A two stage LNA has been designed and developed using a 0.15um commercial GaAs pseudomorphic HEMT technology. The simulated data shows 2.21dB of noise figure with an associated gain of 13.14dB at the frequency operation of 30 GHz. At 3.0V of drain voltage, VDS and -0.20V of gate voltage, VGS; this LNA consume 56mA of total current and achieves 16.10dBm of output P1dB. The layout size is 4.1 × 1.3 mm2.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"30 GHz 2-stage MMIC low noise amplifier using GaAs pseudomorphic HEMT\",\"authors\":\"A. Rasmi, I. M. Azmi, A. Rahim, H. Hsu, E. Chang\",\"doi\":\"10.1109/EDSSC.2013.6628044\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Summary form only given. This paper presents the design and simulated performance of millimeter-wave monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA). A two stage LNA has been designed and developed using a 0.15um commercial GaAs pseudomorphic HEMT technology. The simulated data shows 2.21dB of noise figure with an associated gain of 13.14dB at the frequency operation of 30 GHz. At 3.0V of drain voltage, VDS and -0.20V of gate voltage, VGS; this LNA consume 56mA of total current and achieves 16.10dBm of output P1dB. The layout size is 4.1 × 1.3 mm2.\",\"PeriodicalId\":333267,\"journal\":{\"name\":\"2013 IEEE International Conference of Electron Devices and Solid-state Circuits\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-06-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Conference of Electron Devices and Solid-state Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2013.6628044\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2013.6628044","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

只提供摘要形式。介绍了毫米波单片微波集成电路(MMIC)低噪声放大器(LNA)的设计和仿真性能。采用0.15um商用GaAs伪晶HEMT技术设计和开发了两级LNA。仿真数据显示,在频率为30 GHz时,噪声系数为2.21dB,相关增益为13.14dB。在漏极电压为3.0V时,VDS和栅极电压为-0.20V时,VGS;该LNA的总电流为56mA,输出P1dB为16.10dBm。布局尺寸为4.1 × 1.3 mm2。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
30 GHz 2-stage MMIC low noise amplifier using GaAs pseudomorphic HEMT
Summary form only given. This paper presents the design and simulated performance of millimeter-wave monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA). A two stage LNA has been designed and developed using a 0.15um commercial GaAs pseudomorphic HEMT technology. The simulated data shows 2.21dB of noise figure with an associated gain of 13.14dB at the frequency operation of 30 GHz. At 3.0V of drain voltage, VDS and -0.20V of gate voltage, VGS; this LNA consume 56mA of total current and achieves 16.10dBm of output P1dB. The layout size is 4.1 × 1.3 mm2.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A 116-dB CMOS op amp with repetitive gain boosting and subthreshold operation A novel design of super-capcitor based on black silicon with atomic layer deposition Analysis on the CTLM and LTLM applicability for GaN HEMTs structure alloyed ohmic contact resistance evaluation A PWM controller with table look-up for DC-DC class E buck/boost conversion Failure analysis of output stage due to ESD stress in submicron CMOS technology
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1