{"title":"基于性能和物理约束的多芯片模块系统分区新方法","authors":"Y. Katsura, T. Koide, S. Wakabayashi, N. Yoshida","doi":"10.1109/ASPDAC.1995.486212","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a new and the first MCM system partitioning method considering chip-to-chip delays, chip areas and I/O pins constraints. The proposed method consists of two steps, a clustering step considering the three constraints and an iterative improvement step with mathematical programming. In the first step, we apply two clustering algorithms considering the three constraints and reduce the size of the large MCM system partitioning problem so as to get a solution within a practical computation time. Next, it generates an initial partitioning with 0-1 integer linear programming (ILP) so as to minimize the total wire length. Since there may exist constraint violations in the initial solution, in the second step, we formulate the partitioning problem as a LP problem selecting a maximal independent set and improve it until the total number of cuts is not decreased and the three constraints are satisfied. We also showed that the number of the timing constraints can be reduced by deleting redundant timing constraints. Experimental results showed that the proposed method is able to produce partitions satisfying the three constraints and improves the number of cuts by a 27% on an average and a 30% in maximum over the conventional method [15] considering only two constrains.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A new system partitioning method under performance and physical constraints for multi-chip modules\",\"authors\":\"Y. Katsura, T. Koide, S. Wakabayashi, N. Yoshida\",\"doi\":\"10.1109/ASPDAC.1995.486212\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a new and the first MCM system partitioning method considering chip-to-chip delays, chip areas and I/O pins constraints. The proposed method consists of two steps, a clustering step considering the three constraints and an iterative improvement step with mathematical programming. In the first step, we apply two clustering algorithms considering the three constraints and reduce the size of the large MCM system partitioning problem so as to get a solution within a practical computation time. Next, it generates an initial partitioning with 0-1 integer linear programming (ILP) so as to minimize the total wire length. Since there may exist constraint violations in the initial solution, in the second step, we formulate the partitioning problem as a LP problem selecting a maximal independent set and improve it until the total number of cuts is not decreased and the three constraints are satisfied. We also showed that the number of the timing constraints can be reduced by deleting redundant timing constraints. Experimental results showed that the proposed method is able to produce partitions satisfying the three constraints and improves the number of cuts by a 27% on an average and a 30% in maximum over the conventional method [15] considering only two constrains.\",\"PeriodicalId\":119232,\"journal\":{\"name\":\"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASPDAC.1995.486212\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.1995.486212","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new system partitioning method under performance and physical constraints for multi-chip modules
In this paper, we propose a new and the first MCM system partitioning method considering chip-to-chip delays, chip areas and I/O pins constraints. The proposed method consists of two steps, a clustering step considering the three constraints and an iterative improvement step with mathematical programming. In the first step, we apply two clustering algorithms considering the three constraints and reduce the size of the large MCM system partitioning problem so as to get a solution within a practical computation time. Next, it generates an initial partitioning with 0-1 integer linear programming (ILP) so as to minimize the total wire length. Since there may exist constraint violations in the initial solution, in the second step, we formulate the partitioning problem as a LP problem selecting a maximal independent set and improve it until the total number of cuts is not decreased and the three constraints are satisfied. We also showed that the number of the timing constraints can be reduced by deleting redundant timing constraints. Experimental results showed that the proposed method is able to produce partitions satisfying the three constraints and improves the number of cuts by a 27% on an average and a 30% in maximum over the conventional method [15] considering only two constrains.