采用90纳米CMOS技术的6-b 1-GS/s 30mw ADC

2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI:10.1109/ASSCC.2008.4708725

Yuanching Lien, Jri Lee

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引用次数: 8

摘要

采用90纳米CMOS技术实现了一个带THA的6-b 1-GS/s分位ADC。该电路集成了用于精细ADC的折叠输入以及失调校准和数字校正技术，实现了高达奈奎斯特的大于5.2 ENOB和40 db SFDR，以及1.1 ghz ERBW，功耗仅为30 mW。

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A 6-b 1-GS/s 30-mW ADC in 90-nm CMOS technology

A 6-b 1-GS/s subranging ADC with THA is implemented in 90-nm CMOS technology. This circuit incorporates folded input for the fine ADC as well as offset calibration and digital correction techniques, achieving greater than 5.2 ENOB and 40-dB SFDR up to the Nyquist, and 1.1-GHz ERBW with power consumption of only 30 mW.

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2008 IEEE Asian Solid-State Circuits Conference

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