Shigeya Tanaka, T. Hotta, M. Iwamura, T. Yamauchi, T. Bandoh, A. Hotta, T. Nakano, S. Iwamoto, S. Adachi
{"title":"一种用于70mhz VLSI计算机的BiCMOS 32位执行单元","authors":"Shigeya Tanaka, T. Hotta, M. Iwamura, T. Yamauchi, T. Bandoh, A. Hotta, T. Nakano, S. Iwamoto, S. Adachi","doi":"10.1109/CICC.1989.56730","DOIUrl":null,"url":null,"abstract":"A BiCMOS 32-bit execution has been developed to attain 70-MHz (typical) speed using 1.0-μm BiCMOS technology. The three important components are: (1) an arithmetic unit, which uses a 0.6-ns 8-bit carry propagation circuit; (2) a 2.5-ns 54-W×32-b four-port register file, which uses a BiCMOS sense circuit and dynamic bus drivers; and (3) a flag generator, which uses a novel all-bit-zero generation algorithm and generates in parallel with the arithmetic computation. A CLSI computer has been implemented with the above components, and 70-MHz register-register operation has been achieved","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A BiCMOS 32-bit execution unit for 70 MHz VLSI computer\",\"authors\":\"Shigeya Tanaka, T. Hotta, M. Iwamura, T. Yamauchi, T. Bandoh, A. Hotta, T. Nakano, S. Iwamoto, S. Adachi\",\"doi\":\"10.1109/CICC.1989.56730\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A BiCMOS 32-bit execution has been developed to attain 70-MHz (typical) speed using 1.0-μm BiCMOS technology. The three important components are: (1) an arithmetic unit, which uses a 0.6-ns 8-bit carry propagation circuit; (2) a 2.5-ns 54-W×32-b four-port register file, which uses a BiCMOS sense circuit and dynamic bus drivers; and (3) a flag generator, which uses a novel all-bit-zero generation algorithm and generates in parallel with the arithmetic computation. A CLSI computer has been implemented with the above components, and 70-MHz register-register operation has been achieved\",\"PeriodicalId\":165054,\"journal\":{\"name\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1989.56730\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56730","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A BiCMOS 32-bit execution unit for 70 MHz VLSI computer
A BiCMOS 32-bit execution has been developed to attain 70-MHz (typical) speed using 1.0-μm BiCMOS technology. The three important components are: (1) an arithmetic unit, which uses a 0.6-ns 8-bit carry propagation circuit; (2) a 2.5-ns 54-W×32-b four-port register file, which uses a BiCMOS sense circuit and dynamic bus drivers; and (3) a flag generator, which uses a novel all-bit-zero generation algorithm and generates in parallel with the arithmetic computation. A CLSI computer has been implemented with the above components, and 70-MHz register-register operation has been achieved