ASIC综合成本模型

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186071

J. Lewis, S. Carlson, J. Rau

{"title":"ASIC综合成本模型","authors":"J. Lewis, S. Carlson, J. Rau","doi":"10.1109/ASIC.1990.186071","DOIUrl":null,"url":null,"abstract":"Following a brief introduction to hardware description language (HDL) synthesis and logic synthesis, the impact of synthesis technology on the various aspects of an ASIC product's lifecycle is enumerated. An ASIC synthesis cost model is presented along with the various assumptions and associated justification that have been made. A partial empirical test of the model is made via a set of actual design case studies.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"ASIC synthesis cost model\",\"authors\":\"J. Lewis, S. Carlson, J. Rau\",\"doi\":\"10.1109/ASIC.1990.186071\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Following a brief introduction to hardware description language (HDL) synthesis and logic synthesis, the impact of synthesis technology on the various aspects of an ASIC product's lifecycle is enumerated. An ASIC synthesis cost model is presented along with the various assumptions and associated justification that have been made. A partial empirical test of the model is made via a set of actual design case studies.<<ETX>>\",\"PeriodicalId\":126693,\"journal\":{\"name\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1990.186071\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186071","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

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摘要

在简要介绍硬件描述语言(HDL)合成和逻辑合成之后，列举了合成技术对ASIC产品生命周期各个方面的影响。提出了ASIC综合成本模型，并提出了各种假设和相关的理由。通过一组实际设计案例对模型进行了部分实证检验

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ASIC synthesis cost model

Following a brief introduction to hardware description language (HDL) synthesis and logic synthesis, the impact of synthesis technology on the various aspects of an ASIC product's lifecycle is enumerated. An ASIC synthesis cost model is presented along with the various assumptions and associated justification that have been made. A partial empirical test of the model is made via a set of actual design case studies.<>

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

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