N. Do, L. Tee, S. Hariharan, S. Lemke, M. Tadayoni, W. Yang, M. Wu, JinHo Kim, Yueh-Hsin Chen, C. Su, V. Tiwari, Stephen Zhou, R. Qian, I. Yue
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A 55 nm Logic-Process-Compatible, Split-Gate Flash Memory Array Fully Demonstrated at Automotive Temperature with High Access Speed and Reliability
In this paper, a Flash macro designed with high-density arrays of split-gate (SG) SuperFlash® cells, compatibly embedded in a 55 nm Low Power (LP) logic process is demonstrated with full functionality and excellent reliability at automotive temperature range. This split-gate Flash memory technology can be seamlessly and universally embedded in multiple logic process platforms, and can continually be scaled to 40 nm and smaller lithographically nodes, without compromising performance and reliability.
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