$1.5\mu \mathrm{m}$ Dual Conversion Gain, Backside Illuminated Image Sensor Using Stacked Pixel Level Connections with 13ke-Full-Well Capacitance and 0.8e-Noise

A $1.5\mu \mathrm{m}$ pixel size, 8 mega pixel density, dual conversion gain (DCG), back side illuminated CMOS image sensor (CIS) is described having a linear full-well capacity (FWC) of 13ke- and total noise of 0.8e-RMS at 8x gain. The sensor adopts a world smallest $1.5\mu \mathrm{m}$ pitch, stacked pixel-level connection (SPLC) technology with greater than 8M connections, maximizing fill-factor of the photodiode and dimensions of the associated transistors to achieve a large FWC and low noise performance at the same time. In addition, by allocating transistors into two different layers, the DCG function can be realized with $1.5\mu \mathrm{m}$ pixel size.