基于PUF硬件纠缠和抗侧信道逻辑的65nm CMOS固有安全FPGA

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI:10.1109/ESSCIRC.2019.8902789

B. Erbagci, N. E. C. Akkaya, Cagri Erbagci, K. Mai

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引用次数: 3

摘要

我们提出了一种固有安全的FPGA，它使用基于puf的硬件纠缠配置数据和抗侧信道、自定时逻辑风格。3.14mm x 2.47mm测试芯片采用9金属65nm体CMOS制造，包含安全的10x10瓦FPGA结构(每个6个6输入lut)，在标称1V VDD和室温下运行290MHz。38400位PUF具有较高的唯一性和随机性，误码率< 8.1*10−12。

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An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS

We present an inherently secure FPGA that uses PUF-based hardware-entanglement of the configuration data and a side-channel resistant, self-timed logic style. The 3.14mm x 2.47mm testchip is fabricated in 9-metal 65nm bulk CMOS, contains the secure 10x10 tile FPGA fabric (six 6-input LUTs each), and runs at 290MHz at nominal 1V VDD and room temperature. The 38,400 PUF bits exhibit high uniqueness, randomness, and a BER < 8.1*10−12.

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ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)

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