与LOCOS相比,选择性外延生长(SEG)介电隔离工艺的总工艺成本

J. Hughes, G. Neudeck
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引用次数: 0

摘要

传统的局部氧化硅(LOCOS)器件隔离工艺在半导体工业中得到广泛应用。然而,随着对小于0.18微米及更小器件的需求的增加,LOCOS的应力诱发泄漏电流和器件间距成为严重的限制。浅沟隔离(STI)的使用也得到了发展。然而,最近在选择性外延生长介质隔离(SEG-DI)工艺的改进提供了一种可替代的器件隔离技术。更简单的SEG-DI工艺允许更高的填料密度,并通过消除应力降低泄漏电流。DI-SEG工艺已被证明与LOCOS工艺的成本大致相同。
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The total process cost of selective epitaxial growth (SEG) dielectric isolation process as compared to LOCOS
The traditional local oxidation of silicon (LOCOS) device isolation process is widely used in the semiconductor industry. Yet, as the need for below 0.18 microns and smaller devices increases, the stress induced leakage currents and device spacing of LOCOS becomes a severe limitation. The use of Shallow Trench Isolation (STI) has also been developed. However, recent improvements in the selective epitaxial growth dielectric isolation (SEG-DI) process have provided an alternative device isolation technique. The simpler SEG-DI process allows for higher packing density and reduced leakage current by eliminating stress. The DI-SEG process has been shown to be approximately the same cost as the LOCOS process.
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